Verification Engineers: Learn How Verification Management Can Help You
Background:
Verification of complex SoC (System on Chip) requires tracking of all low-level data (i.e., regression results, functional and code coverage). Usually, verification engineers do this type of tracking manually or using some automation through scripting. Manual efforts in order to get above information while verifying complex SoC may lead us towards the delay in project execution. A verification planning tool can help to reduce such manual efforts and make the tracking process more efficient.
Siemens EDA has such a Verification Planning tool within their Verification Management tool suite. Questa® Verification Management automates the tracking of verification progress by offering the analysis and optimization facilities followed by additional features like trend analysis, back annotation of results, filtration of specific data and other features.
In this webinar we shall discuss steps to use this tracking process along with key features which can reduce the time in verification cycle to track the verification progress.
Who Should Attend?
- Project Manager
- Architect Designer
- RTL Designer
- Verification Engineer
Post the session, the participants will be able to:
- Manage Functional Verification
- Learn Questa VM Solution to
- Manage Data
- Manage Process
- Manage Tools
ON-DEMAND
More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.
