Integrated Circuits: How to Ensure Your TestBench Based Verification Is Complete?
Background:
Even the most carefully designed testbench is inherently incomplete since constrained-random methods cannot hit every corner case. Unfortunately, even after 100%, functional coverage is achieved there can still be showstopper bugs hiding in unimagined state spaces.
Questa Formal Apps statically analyze a design’s behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner. This uncovers design errors that would otherwise be missed or are impractical to find with simulation-based methods.
Tool that will be covered:
Questa Formal Apps
Questa Formal Apps boost verification efficiency and design quality by exhaustively addressing verification tasks that are difficult to complete with traditional methods, and they don’t require formal or assertion-based verification experience.
REGISTER NOW
Who Should Attend?
- Project Leads
- Managers
- FPGA Verification Engineers
Post the session, the participants will be able to understand Formal verification and automated apps and its advantage as:
- Find bugs early
- Improve verification quality
- Increase verification throughput
- High-performance analysis
More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.
