HW Design Engineer: How To Achieve Verification Sign Off For Designs Using HLS
Background:
Adoption of HLS (High-Level Synthesis) continues to grow yet there is also a need for associated HLV (High-Level Verification) methodologies. The motivation for this need is verification at the C++ level (versus RTL) has been shown to reduce overall verification costs by as much as 80%.
This webinar introduces Catapult® “HLS-Aware” C++/SystemC verification tools and flows that will efficiently help find and eliminate bugs early, ensure C→RTL correctness and rapidly close coverage on both the C++ design source and the HLS-generated RTL.
Who Should Attend?
- Project Leads
- Design and Verification teams currently using HLS and want to explore on HLV side
Post the session, the participants will be able to:
- Learn HLV tools and flows
- Learn Using lint and formal tools
- Achieve both code and functional coverage goals on the HLS C++ design source
- Learn the use of SLEC formal methods to confirm equivalence between the generated RTL and the C++ design source
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More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.
