Tessent SiliconInsight
Tessent SiliconInsight provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent ATPG, EDT, BIST, and/or IJTAG test structures.
Tessent SiliconInsight greatly increases productivity for chip designers and test engineers during silicon validation and debug, speeding time-to-market. The solution works in a bench-top environment and connects to any debug, performance, or bring-up board, accessing up to 120 device pins.
Validate test patterns before first silicon using the design in a standard simulator, inject faults, and characterize potential failure scenarios without silicon.
The cell-aware diagnosis capability performs a transistor-level diagnosis to identify defects inside standard cells. This capability leverages the same cell-aware fault model used for cell-aware ATPG and works for any pattern type (stuck-at, transition delay, cell-aware, etc.).
The ATE-Connect technology creates an industry-standard interface to eliminate communication barriers between proprietary, tester-specific software and design-for-test (DFT) platforms.
