An undefined signal occurring at a vital control junction within a design or a register unexpectedly loaded with unpredictable data can rapidly lead to a bewildering and potentially project-halting bug. Regrettably, the treatment of ‘X’ level signals varies between logic synthesis and simulation processes.
The Questa X-Check app is automated to perform exhaustive formal analysis, systematically pinpointing ‘X’ propagation issues within your design. It operates by taking your RTL code and an initialization sequence specification as input, initiating the process.
X-state verification
An undefined signal at a crucial control point in a design, or a register unexpectedly receiving nonsensical data, can rapidly evolve into a complex and project-halting bug. Regrettably, the treatment of ‘X’ level signals varies between logic synthesis and simulation. In logic synthesis, ‘X’ is regarded as a “don’t care,” whereas in simulation, it’s treated as an “unknown.”
Circuit start-up & initialization
- Verify the transition from time 0 to the fully-up state does not leave any ‘X’ values that could potentially corrupt critical design elements or states.
- Ensure that the power-on reset or watchdog circuitry effectively and comprehensively reinitializes the entire circuit.
Low power-related optimizations
- Assign asynchronous resets exclusively to the flip-flops requiring them.
Gate level verification
- Perform an “X unresolved check” to confirm that the register will reliably settle in a predictable logic state during silicon operation.
- Understand the reasons behind the sudden appearance of ‘X’s in post-synthesis gate level netlists, typically arising from simulation ‘X’ pessimism.
