Visualizer is a high-performance, scalable, and context-aware debug solution that supports the complete logic verification flow, including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Its intuitive interface and ease of use help improve debug productivity for complex SoCs and FPGAs.
Questa Visualizer Debug Environment is designed to enhance debug productivity for various design and verification levels including SystemVerilog/UVM, RTL, gate-level, transaction-level, and low-power. It offers synchronized views for waveform analysis, source code review, and connectivity analysis.
RTL debug
In a UVM testbench, the class object handles are essential for managing transactions sent from the sequencer to the driver. This view includes the virtual interface, channel transactions, and color-coded values that correspond to biometric search criteria.
Root cause analysis
With the Visualizer Debug Environment, you can identify unknowns (X values), trace events back in time across multiple clock domains to pinpoint their root causes, and locate the origins of unknowns using the time cone window.
Causality tracing
Automatically highlight signals to trace fan-in connections from a signal back to the next primary input or flip-flop.
Physical connectivity
The Logic Cone Window provides a visual representation of the “physical” connectivity within your design. It enables signal tracing through the design and helps identify the origins of unexpected inputs by displaying RTL objects in a graphical view.
