Visualizer is a high-performance and scalable context-aware debug tool that supports the entire logic verification flow, including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. With an intuitive and user-friendly interface, Visualizer greatly enhances the debug productivity of complex SoCs and FPGAs.

 

Questa Visualizer Debug Environment is designed to enhance debug productivity for various types of design and verification, including SystemVerilog/UVM, transaction-level, RTL, gate-level, and low-power. Its features include synchronized views for waveform analysis, source code examination, and connectivity visualization.

RTL debug

The UVM testbench can now utilize class object handles from the driver, showing all the transactions that were sent from the sequencer. The Virtual interface and transactions from the channel are also displayed, with the added feature of biometric search color-coding for easier analysis of values.

biometric search
questa verification iq root cause analysis

Root cause analysis

With the Visualizer Debug Environment, you can easily locate unknown values (X values), track the source of an event by tracing it back through multiple clock domains, and identify the origin of unknown values using the time cone window.

Causality tracing

Visualizer provides an automatic fan-in display feature that highlights signals and traces them back to the next primary input or flip flop, making it easy to analyze the signal’s behavior.

Causality tracing
physical connectivity

Physical connectivity

The logic cone window in the Visualizer Debug Environment provides a graphical representation of RTL objects in your design, enabling you to explore the physical connectivity of your design and trace signal propagation. It also helps you identify the source of unexpected inputs, making debug more efficient and effective.