Utilizing both the “specification” RTL and the “implementation” RTL as inputs, the Questa SLEC formal app systematically contrasts the two code blocks through a comprehensive formal analysis. This process doesn’t necessitate expertise in formal methods or property specification languages.
Modern designs heavily depend on intricate industry-standard interfaces that require verification to ensure IP compatibility and overall system functionality. Regardless of whether an interface is employed as-is or customized to distinguish the final product, the integration of even well-established IP can lead to unforeseen challenges.
Automated, exhaustive SLEC
The Questa “SLEC” app employs formal analysis to meticulously compare the “Specification” and “Implementation” RTL, detecting any disparities in their output behavior across all inputs and throughout all time intervals. This process doesn’t demand expertise in formal methods or property specification languages.
Exhaustive results
- Achieves over 10 times faster results compared to simulation for specific use cases.
- Doesn’t necessitate a testbench or formal expertise.
- Delivers impressive run-time performance and scalability.
