Beneath the surface, PropCheck’s top-tier, high-capacity, and high-throughput engines synergize in real time, capitalizing on their individual strengths to accelerate the verification process.
Questa PropCheck serves as the ideal tool to expedite bug detection, error rectification, and coverage closure. It effortlessly verifies designs by comparing their behavior to the intended behavior outlined in the assertions, thereby identifying all reachable design states starting from the initial state.
Define the intended behavior
Even meticulously designed constrained-random testbenches cannot explore every aspect of a design’s state space. The reality is that simulation-based verification is inherently partial, even for relatively modest Design Under Tests (DUTs). The process of developing a simulation testbench can extend over several weeks, creating an opening for intricate bugs to be inadvertently incorporated into the IP.
Advantages
- Mathematically demonstrate compliance of the DUT with specifications for all inputs, at all times.
- Address all facets of the DUT with top-notch performance in the industry.
- Seamlessly integrated with Questa Verification Management through UCDB (Unified Coverage DataBase).
