The immediate hurdle arises when you suspect a particular cluster or IP as the potential source of issues. The challenge lies in establishing specific initial test conditions, probes, and constrained-random stimuli to access the internal aspects of the Design Under Test (DUT), particularly when the SoC is in its final, fully realized state.
After synthesizing assertions outlining the intended behaviors within the Design Under Test (DUT) on the hardware-assisted verification platform, the Questa Post-Silicon Debug app utilizes the formal-based Questa Property Checking app (PropCheck) to pinpoint the underlying cause of any observed failures.
Leverage formal analysis
The Questa Post-Silicon Debug app combines formal analysis with property synthesis to swiftly provide the necessary visibility for identifying and addressing bugs within the deep logic of the SoC. It also ensures that any fixes implemented do not introduce new issues elsewhere.
Complex SoCs are challenging
- Observe a scenario in the lab.
- Capture the observed scenario through an assertion.
- Identify potential failures using the assertion.
- Generate waveform representations of events leading up to these failures.
