The formal engines achieve comprehensive verification of both static and dynamic connections within a matter of hours, a significantly shorter timeframe compared to the weeks typically needed with test bench simulation-based methods.
Utilizing a clear, human and machine-readable spreadsheet in conjunction with RTL code as input, the Questa Connectivity Check app automates formal technology to perform exhaustive verification of both static and dynamic connections of all types.
Ease of use
Automatically generates all necessary assertions based on your CSV or XML connectivity specifications and presents them in a user-friendly tabular format.
Thorough coverage
Conducts verification of on-chip bus, inter-block, control signal, clock, and reset connections at both the sub-system and SoC levels. This verification process covers all modes of operation comprehensively.
Speed
Conducts thorough verification of all static and dynamic connections within a few hours. It treats the interior areas of IPs in your RTL as “black boxes,” concentrating solely on connectivity assessment.
