Siemens’ flagship FPGA synthesis solution, featuring extensive optimizations, debug and validation capabilities, and close connection with the Siemens FPGA flow. With a user-friendly validation environment, it offers various unique features that help every designer to attain design closure faster.
Mitigate SEEs & Ensure Functional EquivalenceMitigate SEEs & Ensure Functional Equivalence
An integrated flow from design generation in C++/SystemC/HDL through design synthesis, design verification and validation, and PCB design is required for successful FPGA design. As a consequence, the best FPGA implementation fits all design criteria and allows designers to meet standards such as DO-254.
Precision RTL Plus includes a number of capabilities for DO-254-certified safety-critical designs in the military-aerospace arena. These include verified repeatability of synthesis results, design assurance synthesis, and DO-254 certification made possible by close interaction with Siemens FPGA design flow.
Integration with Siemens FPGA Flow
Siemens EDA features the industry’s only comprehensive FPGA design pipeline, with Precision RTL Plus at the heart. It is tightly coupled with the following flows:
- High-level Synthesis with Catapult
- Design reuse with HDL Designer
- Equivalence checking with FormalPro
- Requirements tracking with ReqTracer
- FPGA-PCB co-design with I/O Optimizer
FPGA Resource Manager
FPGAs today have a plethora of specialized resources, such as DSPs and RAMs. However, making the best use of these resources is difficult. Precision RTL Plus is a one-of-a-kind solution that includes an FPGA Resource Manager, a graphical tool for managing embedded resources, and doing what-if analysis to get the optimum performance and area.
