High-Level Synthesis (HLS) and High-Level Verification (HLV) by Catapult revolutionise the game.
Concerned that your next RTL project may be late? Will your new “secret sauce” design be sufficient, or will it consume too much power? How will you ensure that it is functionally valid and ideally constructed before committing to RTL? Catapult High-Level Synthesis (HLS) & High-Level Verification (HLV) alters the game.
RTL productivity has slowed, particularly for new and complicated value-add blocks. The design and verification problems of designing new and novel architectures that give advantages in silicon for Wireless, 5G, ML, or Video/Image processing are making design teams’ lives difficult.
Will your hardware have an impact on system performance? Did you select the correct fundamental memory architecture? Or did you discover during system integration and testing that real-world performance was insufficient?
Bugs discovered late in RTL entail wasted opportunities, less competitive silicon, tape out delays, and ECO difficulties. HLS design and verification ensures correct-first-time RTL designs while lowering server and tool costs.
It is difficult to achieve an appropriate combination of Performance, Power, and Area for your design objectives. You may miss a product cycle if you have insufficient performance, power, or area. Use HLS to create better and faster.
Siemens Catapult Synthesis solutions provide support for the C++ and SystemC programming languages, FPGA and ASIC independence, ASIC power estimation and optimization, and the most recent advances in Physically aware multi-VT area and performance optimization.
A complete HLS tool that meets all of your requirements for the trickiest ASIC and FPGA designs.
When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.
Catapult maintains up with shrinking geometries with design adaptability, tangible downstream data, and outstanding QoR.
Everything you require to quicken the flow of high-level verification. Utilizing Design Checking, Code and Functional Coverage along with Formal, you can cut the time and cost of verification by up to 80%.
Before synthesis, use lint and formal analysis to confirm the accuracy of your HLS designs. Avoid coding for HLS’s potential design and quality-of-results difficulties.
Provides HLS-aware code coverage, including statement, branch, FEC, toggle, and array access. Functional coverage inspired by SV with support for cover groups, cover points, bins, and crosses.
Formally identify errors, ambiguities, unfavourable design difficulties, and user constraint issues early in the HLS process. Even with timing and interface variations The verification and coverage closing flow are made possible using Catapult Formal.
Using SLEC, compare the accuracy of RTL to your High-Level models. allowing for the demonstration of the consistency between a specification’s implementation despite changes in language, timing, or abstraction.
