Catapult provides cutting-edge HLS tools for FPGA, eFPGA, and ASIC with industry-leading C++ and SystemC support. With solutions for great Quality Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage, Catapult will hasten your success.
Siemens’ Catapult Synthesis systems offer support for the C++ and SystemC programming languages, FPGA and ASIC independence, ASIC power estimation and optimization, and the most recent advances in physically aware multi-VT area and performance optimization.
A complete HLS tool that meets all of your requirements for the trickiest ASIC and FPGA designs.
When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.
Catapult maintains up with shrinking geometries with design adaptability, tangible downstream data, and outstanding QoR.
